june 21, 201 3 | final | v1.09 1 digital multi-phase buck controller ir3541 chl8325a/b features ? 5-phase dual output pwm controller ? phases are flexibly assigned between loops 1 & 2 ? intel? vr12, amd? 400khz & 3.4mhz svi and memory modes ? dual ocp support for i-spike enhanced amd cpus ? smb_alert pin for servers ? pmbus address pin or variable gate drive (ir3541/chl8325a) ? 2 nd temperature sense for vr12 desktop (chl8325b) ? overclocking & gaming mode with vmax setting ? switching frequency from 200khz to 1.2mhz per phase ? ir efficiency shaping features including variable gate drive (ir3541/chl8325a only) and dynamic phase control ? programmable 1-phase or 2-phase for light loads and active diode emulation for very light loads ? ir adaptive transient algorithm (ata) on both loops minimizes output bulk capacitors and system cost ? auto-phase detection with auto- co mpensation ? per-loop fault protection: ovp, uvp, ocp, otp, cfp ? i2c/smbus/pmbus system interface for telemetry of temperature, voltage, current & power for both loops ? non -volatile memory (nvm) for custom configuration ? compatible with ir atl and 3.3v t ri -state drivers ? +3.3v supply voltage; -20oc to 85oc ambient operation ? pb -free, rohs, 6x6 40-pin qfn , msl2 package applications ? intel ? vr12 & amd? svi based systems ? ddr memory with vtt tracking ? overclocked & gaming platforms description the ir3541 and chl8325a/b are dual-loop digital multi-phase buck controllers that drive up to 5 phases. the ir3541 and chl8325a/b are fully intel? vr12 and amd? svi compliant on both loops and provides a vtt tracking function for ddr memory. nvm storage saves pins and enables a small package size. the ir3541 and chl8325a/b include the ir efficiency shaping technology to deliver exceptional efficiency at minimum cost across the entire load range. ir variable gate drive optimizes the mosfet gate drive voltage as a function of real-time load current. ir dynamic phase control adds/drops active phases based upon load current. the ir3541 and chl8325a/b can be configured to enter 1-phase operation and active diode emulation mode automatically or by command. is unique adaptive transient algorithm (ata), based on proprietary non-linear digital pwm algorithms, minimizes output bulk capacitors. the i2c/pmbus interface can communicate with up to 16 ir3541 and chl8325a/b based vr loops. device configuration and fault parameters are easily defined using the ir intuitive power designer (dpdc) gui and stored in on -chip nvm. the ir3541 and chl8325a/b also include numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying vrd design and enabling fastest time- to - aket ith its set -and- foget methodology. pin diagram figure 1: ir3541 package top view downloaded from: http:///
june 21, 201 3 | final | v1.09 2 digital multi-phase buck controller ir3541 chl8325a/b ordering information ir3541m ? ? ? ? ? ? ? ? ? chl8325 ? D ? ? ? ? ? figure 2: ir3541 package top view, enlarged package packing qty part number programming qfn tr= 3000 ty=4900 ir3541mtrpbf ir3541 mt ypbf default qfn tr= 3000 ir3541mxxyytrp 1 customer configuration notes: 1. customer specific configuration file, where xx = customer id and yy = configuration file (codes assigned by ir marketing). package packing qty part number qfn t= 3000 ty=4900 CHL8325A-00CRT CHL8325A-00CRTy qfn t= 3000 chl8325a-xxcrt 1 qfn t=30 00 ty=4900 chl8325b-00crt chl8325b-00crty qfn t= 3000 chl8325b-xxcrt 1 notes: 1. indicates a customer specific configuration file. smb_dio pwm5 enable vrtn rcsm isen5 isen4 isen3 vsen smb_clk pwm4 vr_ready_l1 1 / pwrgd 2 irtn3 irtn4 irtn5 rcsp tsen vr_hot# 1 / vrhot_icrit# 2 pwm3 smb_alert# v18a rres vcc isen2 isen1 irtn1 irtn2 pwm2 pwm1 rcsm_l2 rcsp_l2 var_gate_pm_addr (chl8325 a ) tsen2 (chl8325 b ) sv_dio 1 / svd 2 sv_clk 1 / svc 2 sv_alert 1 / vfixen 2 vr_ready_l2 1 / pwrok 2 vcc vinsen vrtn_l2 vsen_l2 1 2 7 8 5 6 3 4 10 9 30 29 24 23 26 25 28 27 21 22 41 gnd chl8325a/b 40 pin 6x6 qfn top view 12 16 14 19 13 17 15 20 18 11 39 35 37 32 38 34 36 31 33 40 notes1 pin definition in intel & mpol modes 2 pin definition in amd mode figure 3: chl8325a/b package top view, enlarged t C tape & reel / ty - tray r C package type (qfn) c C operating temperature, commercial xx C configuration file part C a : chl8325a b : chl8328b p/pbf C lead free tr C tape & reel / ty - tray yy C configuration file id xx C customer id package type (qfn) downloaded from: http:///
june 21, 201 3 | final | v1.09 3 digital multi-phase buck controller ir3541 chl8325a/b functional block diagram isen1 irtn1 isen2 irtn2 isen3 irtn3 isen4 irtn4 isen5 irtn5 tsen vinsen voltage adc vsen vrtn control and monitoring pwm generator vout1_error vout2_error pwm1 pwm2 pwm3 pwm4 pwm5 reference, oscillator, state control, interfaces, registers and nvm smb_dio adc clocks mux clocks phase_period_1 phase_period_2 v3_3 iout vin temp fault bus system clock iout vin temp vout fault bus system clock vid_1 vid_2 current adc itot_1 itot_2 ip1 ip2 ip3 ip4 ip1 ip2 ip3 ip4 ip5 mode control ip5 var_gate_pm_addr (chl8325a) ldo vcc 1.8v v18a smb_clk smb_alert# en vr_hot# 1 /vrhot_icrit# 2 vr_ready_l1 1 /pwrgd 2 vr_ready_l2 1 /pwrok 2 phase_ period_1 phase_ period_2 rres rcsp rscm afe_1 vid_1 sv_alert# 1 /vfixen 2 sv_clk 1 /svc 2 sv_dio 1 /svd 2 notes 1 pin definition in intel & mpol modes 2 pin definition in amd mode tsen2 (chl8325b) vsen_l2 vrtn_l2 rcsp_l2 rscm_l2 afe_2 itot_2 vid_2 monitor adc figure 4: ir3541 and chl8325a/b functional block diagram (ir3541 & chl8325a) downloaded from: http:///
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